1. Technical Field
The present invention relates in general to cache controllers in data processing systems and in particular to cache controllers which layer cache and architectural specific functions. Still more particularly, the present invention relates to supporting straightforward extension of nonshared cache controller implementations to shared implementations, with simple resolution of associated flow rate issues.
2. Description of the Related Art
Data processing systems which utilize a level two (L2) cache typically include a cache controller for managing transactions affecting the cache. Such cache controllers are conventionally implemented on a functional level, as depicted in FIG. 7. For example, a cache controller 702 may include logic 704 for maintaining the cache directory, logic 706 for implementing a least recently used (LRU) replacement policy, logic for managing reload buffers 708, and logic for managing store-back buffers 710. In traditional implementations, the cache is generally very visible to these and other architectural functions typically required for cache controllers, with the result that cache controller designs are specific to a particular processors such as the PowerPC.TM., Alpha.TM., or the x86 family of processors.
The basic controller structure depicted in FIG. 7 is employed in both nonshared and shared cache controller designs. Nonshared cache controllers manages transactions between a single upstream processor and a nonshared cache. Shared cache controllers, which manage transactions to a cache shared by two or more processors, are difficult to design but have been successfully implemented. Because of the extensive interlocks required, controller designs for a single upstream processor are virtually useless when designing a controller for a shared cache. The logic required for nonshared cache controllers is already complex for many processors and bus architectures because of the numerous special cases which must be accommodated. The logic complexity increases exponentially as additional upstream processors are added and additional interlock logic for coordination becomes necessary. In particular, a substantial portion of the complexity in a shared cache design derives from the requirement--unique to shared cache designs--that the cache controller be capable of responding to a plurality of operations initiated by different processors in the same cycle. For a nonshared cache, only one operation may be initiated within a given cycle. Under the prior art approach, nonshared cache controller designs may not be easily reused in shared cache controllers, but require extensive and laborious design modifications and enhancements for successful transition to a shared controller design.
An additional problem with prior art designs relates to operation flow rate. Typically operations are initiated at a certain rate. In traditional implementations, operations initiated by an upstream processor or processors generally cannot be cancelled or ignored by the cache controller. The cache controller must respond to the operation, even if only to indicate that the operation should be retried later. Therefore, cache controllers are designed to respond to operations at the rate at which they are initiated by an upstream processor or processors. Thus, if a controller supports a single upstream processor which initiates operations at a given flow rate, cache controller 702 must respond to operations at that flow rate. For example, where a bus is defined to be capable of producing an operation once every three cycles, the cache controller is also designed to respond to operations at a rate of one every three cycles. Similarly, shared cache controllers are designed to respond to operations at a cumulative flow rate for upstream processors (that is, equal to the flow rate of all operations initiated by processors sharing the subject cache). Such operational speed requirements, imposed on necessarily complex logic, present a substantial design obstacle.
It would be desirable, therefore, to implement a cache controller which permits straightforward extension of a nonshared controller design to a shared design. It would further be advantageous to provide a cache controller design permitting uncomplicated resolution of the operation flow rate issues associated with implementing a shared cache controller.